JPH0426545U - - Google Patents
Info
- Publication number
- JPH0426545U JPH0426545U JP1990067997U JP6799790U JPH0426545U JP H0426545 U JPH0426545 U JP H0426545U JP 1990067997 U JP1990067997 U JP 1990067997U JP 6799790 U JP6799790 U JP 6799790U JP H0426545 U JPH0426545 U JP H0426545U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- board
- holes
- circuit component
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990067997U JPH0426545U (en]) | 1990-06-27 | 1990-06-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990067997U JPH0426545U (en]) | 1990-06-27 | 1990-06-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0426545U true JPH0426545U (en]) | 1992-03-03 |
Family
ID=31602068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990067997U Pending JPH0426545U (en]) | 1990-06-27 | 1990-06-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0426545U (en]) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002334948A (ja) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | 半導体パッケージ、半導体素子搭載用基板及びそれらの製造方法 |
| JP2002334951A (ja) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | 半導体素子搭載用基板及び半導体パッケージ |
| JP2002334949A (ja) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | 半導体パッケージ及び半導体素子搭載用基板の製造方法 |
-
1990
- 1990-06-27 JP JP1990067997U patent/JPH0426545U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002334948A (ja) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | 半導体パッケージ、半導体素子搭載用基板及びそれらの製造方法 |
| JP2002334951A (ja) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | 半導体素子搭載用基板及び半導体パッケージ |
| JP2002334949A (ja) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | 半導体パッケージ及び半導体素子搭載用基板の製造方法 |